1. Field of the Invention
This invention relates to phase-locked loops and more particularly to phase error correction in phase-locked loops.
2. Description of the Related Art
Phased-locked loops (PLLs) control an oscillator output signal so that it maintains a desired relationship with an input reference signal. The desired relationship may be to maintain a particular phase/frequency relationship with the input reference signal. PLL circuits are commonly used to multiply and divide the input reference signal. Some PLL implementations restrict the PLL output signal to be an integer multiple of an input reference signal supplied to the PLL. Other PLL implementations provide more versatility and allow the PLL output signal to be a non-integer multiple of the input reference signal. FIG. 1 illustrates one such PLL known as a fractional-N phase-locked loop.
The PLL 100 compares the reference signal supplied on node 101 to a feedback signal supplied on node 103 in phase/frequency detector 105. That difference is used to drive the charge pump and loop filter 107, which in turn supplies the voltage controlled oscillator 109 with a control signal to adjust its output based on the comparison of the input reference signal and the feedback signal. Fractional-N PLLs typically have a delta sigma modulator 113 that receives a rational number M as a divide ratio that corresponds to the desired output frequency and supplies a sequence of integers M′ to the feedback divider 111. The sequence of integers averages the divide ratio M and the divider adjusts its divide value based on the received sequence. In that way, the PLL outputs a signal having an average frequency corresponding to M. However, while the average frequency output may be correct, phase errors are introduced into the VCO output signal because the divide ratio M′ is not equal to the desired divide ratio M.
Since the sequence of integers provided to the feedback divider is known, the error introduced into the system, i.e., the difference between the divider value M′ generated by the delta sigma modulator and the desired divider value M can be determined. That error shows up at the front end of the phase-locked loop at the phase/frequency detector 105. By utilizing the error introduced into the system by the fractional-N divider, i.e., the difference between the M and M′, a phase error correcting circuit (PEC) can determine the phase error introduced and supply to the charge pump a phase error correction signal that offsets the introduced error at the front end of the PFD.
Generally, the goal of phase error correction is to generate a phase error correction signal that closely matches the actual phase error. The phase error correction signal may first be determined digitally. Typically a digital to analog converter circuit then converts the digital representation of the phase error correction signal to an analog signal that can used by the charge pump to offset the phase error. However, the digital phase error correction signal generally has significantly more bits than can be converted accurately or quickly enough by a digital to analog converter (DAC), so the digital phase error correction signal is typically truncated prior to being supplied to the DAC. However, simply truncating the phase error correction signal causes the phase error correction signal to have a noise spectrum that has significant energy in frequency bands of interest. To reduce this problem, some approaches have utilized noise shaping to improve the noise spectrum of the quantized phase error correction signal.
However, for certain applications some noise shaping techniques may not meet stringent noise specifications. Accordingly, it would be desirable to provide improved techniques for phase error correction.